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IC1110-F128LQ USB Flash Card Reader Controller
1.
- - -
FEATURES
High speed 8-bit micro-controller with 4 system clocks per machine cycle Instruction-set compatible with MCS-51 Embedded 32K-byte program FLASH ROM for product quick delivery. In System Programming, ISP is supported by either USB or I2C port. - - Master/Slave IIC and UART/RS-232 interface for external device communication. Compact Flash Card and IDE bus interface complies with Compact Flash Specification Rev.1.4 "True IDE Mode", which is compatible with most hard disk drives and IBM micro drive. - Smart Media Card/NAND type flash chip interface complies with Smart Media Specification Rev.1.1 and Smart Media Identify Number Specification Version 1.1 - - - - - - - - Multi Media Card interface complies with Multi Media Card System Specification Rev. 1.4. SD Card interface complies with SD Card System Specification Rev. 1.0 Memory Stick Card interface compiles with Memory Stick Standard Format Specifications version 1.3 Built-in hardware ECC (Error Correction Code) check for Smart Media Card/NAND type flash chip. Built-in hardware CRC check for MMC and SD cards. Dedicated pins reserved for MP3 decoder interface. 3.0~3.6V supply. 128LQFP packages is available.
- - - - - - -
Built in fixed address 256 bytes data RAM. Built in floating address 4608 bytes data RAM Optional external floating data RAM space with up to 32M+32K bytes. Extra 1K bytes CPU data RAM space available by disable central control block function. System power saving mode ready, idle & power down modes. Three programmable 16-bit timer/counter and watchdog timer. Compliant with USB Specification Rev.1.1 supports full speed (12Mbits/sec), one device address and four endpoints. (Including control, interrupt, bulk in and bulk out endpoints)
-
Built in ICSI in-house bi-directional parallel port for quick data transfer. Both master and slave modes are supported.
-
Built in SDRAM interface for supporting memory size up to 256M bits.
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2. PIN INFORMATION
2.1.1.
PIN FUNCTION DESCRIPTION Signal Name PP_D0 PP_D1 PP_D2 PP_D3 PP_D4 PP_D5 PP_D6 PP_D7 PP_RW PP_RDY IO IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_PU IO_PU Pin Number 21 39 61 67 93 96 109 126 25 57 Description Parallel port data bus bit 0. Share with PC0 Parallel port data bus bit 1. Share with PC1 Parallel port data bus bit 2. Share with PC2 Parallel port data bus bit 3. Share with PC3 Parallel port data bus bit 4. Share with PC4 Parallel port data bus bit 5. Share with PC5 Parallel port data bus bit 6. Share with PC6 Parallel port data bus bit 7. Share with PC7 Parallel port read/write trigger, active high. Share with P31 Parallel port READY signal, active high. Share with P30
Function Parallel Port
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Function Signal Name PP_EN PP_DIR CF/IDE Card CF_D0 CF_D1 CF_D2 CF_D3 CF_D4 CF_D5 CF_D6 CF_D7 CF_D8 CF_D9 CF_D10 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_A0 CF_A1 CF_A2 CF_RDn CF_WRn CF_RSTN CF_CS0 CF_CS1 CF_CD1 CF_CD2 CF_INTREQ SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_CD1 SM_CLE SM_RNB SM_ALE SM_RD SM_WR SM_WP MM_DAT0 MM_DAT1 MM_DAT2 MM_DAT3 IO IO_TR IO_PU IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_PU IO_PU IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_PU IO_PU IO_PU IO_PU IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR Pin Number 86 88 30 35 40 49 62 69 70 76 84 90 107 108 110 112 120 124 36 37 1 41 43 59 121 12 19 24 16 21 39 61 67 93 96 109 126 13 88 45 52 23 71 80 21 39 61 67 Description Parallel port enable, active high. Share with P35 Parallel port direction control. Share with P45 CF card data bus bit 0. Share with P70 CF card data bus bit 1. Share with P71 CF card data bus bit 2. Share with P72 CF card data bus bit 3. Share with P73 CF card data bus bit 4. Share with P74 CF card data bus bit 5. Share with P75 CF card data bus bit 6. Share with P76 CF card data bus bit 7. Share with P77 CF card data bus bit 8. Share with P90 CF card data bus bit 9. Share with P91 CF card data bus bit 10. Share with P92 CF card data bus bit 11. Share with P93 CF card data bus bit 12. Share with P94 CF card data bus bit 13. Share with P95 CF card data bus bit 14. Share with P96 CF card data bus bit 15. Share with P97 CR card address bit 0. Share with P16 CR card address bit 1. Share with P17 CR card address bit 2. Share with P80 Read strobe pin to CF card. Share with P12 Write strobe pin to CF card. Share with P13 Reset pin to CF card, active low. Share with P11 Card select pin 0. Share with P15 Card select pin 1. Share with P81 Card detection pin 1. Share with P82 Card detection pin 2. Share with P83 CF card interrupt request. Share with P10 SM card data bus bit 0. Share with PC0 SM card data bus bit 1. Share with PC1 SM card data bus bit 2. Share with PC2 SM card data bus bit 3. Share with PC3 SM card data bus bit 4. Share with PC4 SM card data bus bit 5. Share with PC5 SM card data bus bit 6. Share with PC6 SM card data bus bit 7. Share with PC7 Card detect pin, active low. Share with P84 Command latch enable, active high. Share with P45 Ready/Busy. Share with P46 Address latch enable, active high. Share with P47 Read enable, active low. Share with P85 Write enable, active low. Share with P86 Write protect, active low. Share with P87 MMC/SD card data bus bit 0. Share with PC0 SD card data bus bit 1. Share with PC1 SD card data bus bit 2. Share with PC2 SD card data bus bit 3. Share with PC3
SM Card
MMC/SD Card
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Function Signal Name MM_CLK MM_CMD MS Card MS_BS MS_SCLK MS_INS MS_SDIO DRM_DQ0 DRM_DQ1 DRM_DQ2 DRM_DQ3 DRM_DQ4 DRM_DQ5 DRM_DQ6 DRM_DQ7 DRM_A0 DRM_A1 DRM_A2 DRM_A3 DRM_A4 DRM_A5 DRM_A6 DRM_A7 DRM_A8 DRM_A9 DRM_A10 DRM_A11 DRM_A12 DRM_A13 DRM_A14 DRM_CLK DRM_CAS DRM_RAS DRM_WE DRM_CSN DRM_CKE DRM_UDQM DRM_LDQM MP3_D MP3_CLK MP3_REQ IIC_CL IIC_DA TXD RXD AD0 IO IO_PU IO_PU IO_PU IO_PU IO_PU IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_PU IO_PU IO_PU IO_PU IO_PU Pin Number 68 73 46 54 65 93 16 59 41 43 50 121 36 37 30 35 40 49 62 69 70 76 84 90 107 108 110 112 120 1 12 124 23 71 98 14 17 89 118 128 25 57 25 57 6 Description MMC/SD card clock. Share with P43 MMC/SD card command. Share with P44 MS card bus stat signal. Share with P40 MS card clock signal. Share with P41 MS card insertion/extraction detect. Share with P42 MS card data bus. Share with PC4 I/O data bit0. Share with P10 I/O data bit1. Share with P11 I/O data bit2. Share with P12 I/O data bit3. Share with P13 I/O data bit4. Share with P14 I/O data bit5. Share with P15 I/O data bit6. Share with P16 I/O data bit7. Share with P17 Address bit 0. Share with P70 Address bit 1. Share with P71 Address bit 2. Share with P72 Address bit 3. Share with P73 Address bit 4. Share with P74 Address bit 5. Share with P75 Address bit 6. Share with P76 Address bit 7. Share with P77 Address bit 8. Share with P90 Address bit 9. Share with P91 Address bit 10. Share with P92 Address bit 11. Share with P93 Address bit 12. Share with P94 Address bit 13. Share with P95 Address bit 14. Share with P96 Clock output. Share with P80 Column address strobe. Share with P81 Raw address strobe. Share with P97 Write enable. Share with P85 Chip select. Share with P86 Clock enable. Share with P34 Upper byte I/O mask bit. Share with PA5 Lower byte I/O mask bit. Share with PA6 MP3 bit stream output. Share with PA0 MP3 bit stream transmits clock. Share with PA2 MP3 bit stream request, high active. Share with PA1 IIC clock. Share with P31 IIC data. Share with P30 Serial output. Share with P31 Serial input. Share with P30 Address and data for external ROM/RAM. Share with P00
SDRAM
MP3
Master/Slave IIC
UART
EXT ROM/RAM
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Function Signal Name AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 WR RD Timer/counter T0 T1 T2 T2EX INT0 INT1 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 P00 P01 P02 P03 P04 P05 P06 P07 IO IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_TR IO_TR IO_TR IO_TR IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU Pin Number 9 26 29 34 38 44 53 58 60 85 95 111 119 123 125 94 78 98 86 16 59 27 55 6 9 26 29 34 38 44 53 58 60 85 95 111 119 123 125 6 9 26 29 34 38 44 53 Description Address and data for external ROM/RAM. Share with P01 Address and data for external ROM/RAM. Share with P02 Address and data for external ROM/RAM. Share with P03 Address and data for external ROM/RAM. Share with P04 Address and data for external ROM/RAM. Share with P05 Address and data for external ROM/RAM. Share with P06 Address and data for external ROM/RAM. Share with P07 Address for external ROM/RAM. Share with P20 Address for external ROM/RAM. Share with P21 Address for external ROM/RAM. Share with P22 Address for external ROM/RAM. Share with P23 Address for external ROM/RAM. Share with P24 Address for external ROM/RAM. Share with P25 Address for external ROM/RAM. Share with P26 Address for external ROM/RAM. Share with P27 Memory write for external RAM. Share with P36 Memory read for external RAM. Share with P37 External pin for timer 0. Share with P34 External pin for timer 1. Share with P35 External counter clock input for timer 2. Share with P10 External counter enable for timer 2. Share with P11 External interrupt 0. Share with P32 External interrupt 1. Share with P33 Port 5 bit 0. Share with P00 Port 5 bit 1. Share with P01 Port 5 bit 2. Share with P02 Port 5 bit 3. Share with P03 Port 5 bit 4. Share with P04 Port 5 bit 5. Share with P05 Port 5 bit 6. Share with P06 Port 5 bit 7. Share with P07 Port 6 bit 0. Share with P20 Port 6 bit 1. Share with P21 Port 6 bit 2. Share with P22 Port 6 bit 3. Share with P23 Port 6 bit 4. Share with P24 Port 6 bit 5. Share with P25 Port 6 bit 6. Share with P26 Port 6 bit 7. Share with P27 Port 0 bit 0. Port 0 bit 1. Port 0 bit 2. Port 0 bit 3. Port 0 bit 4. Port 0 bit 5. Port 0 bit 6. Port 0 bit 7.
EXT interrupt
AUX IO
GPIO
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Function Signal Name P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 IO IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_PU IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_PU IO_PU IO_PU IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR Pin Number 16 59 41 43 50 121 36 37 58 60 85 95 111 119 123 125 57 25 27 55 98 86 94 78 46 54 65 68 73 88 45 52 30 35 40 49 62 69 70 76 1 12 19 24 13 23 71 80 84 90 107 Description Port 1 bit 0. Port 1 bit 1. Port 1 bit 2. Port 1 bit 3. Port 1 bit 4. Port 1 bit 5. Port 1 bit 6. Port 1 bit 7. Port 2 bit 0. Port 2 bit 1. Port 2 bit 2. Port 2 bit 3. Port 2 bit 4. Port 2 bit 5. Port 2 bit 6. Port 2 bit 7. Port 3 bit 0. Port 3 bit 1. Port 3 bit 2. Port 3 bit 3. Port 3 bit 4. Port 3 bit 5. Port 3 bit 6. Port 3 bit 7. Port 4 bit 0. Port 4 bit 1. Port 4 bit 2. Port 4 bit 3. Port 4 bit 4. Port 4 bit 5. Port 4 bit 6. Port 4 bit 7. Port 7 bit 0. Port 7 bit 1. Port 7 bit 2. Port 7 bit 3. Port 7 bit 4. Port 7 bit 5. Port 7 bit 6. Port 7 bit 7. Port 8 bit 0. Port 8 bit 1. Port 8 bit 2. Port 8 bit 3. Port 8 bit 4. Port 8 bit 5. Port 8 bit 6. Port 8 bit 7. Port 9 bit 0. Port 9 bit 1. Port 9 bit 2.
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Function Signal Name P93 P94 P95 P96 P97 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PLL FILTER IO IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_TR IO_PU IO_TR O Pin Number 108 110 112 120 124 89 128 118 20 106 14 17 22 28 31 42 51 56 72 74 77 21 39 61 67 93 96 109 126 79 82 87 97 117 122 103 Description Port 9 bit 3. Port 9 bit 4. Port 9 bit 5. Port 9 bit 6. Port 9 bit 7. Port A bit 0. Port A bit 1. Port A bit 2. Port A bit 3. Port A bit 4. Port A bit 5. Port A bit 6. Port A bit 7. Port B bit 0. Port B bit 1. Port B bit 2. Port B bit 3. Port B bit 4. Port B bit 5. Port B bit 6. Port B bit 7. Port C bit 0. Port C bit 1. Port C bit 2. Port C bit 3. Port C bit 4. Port C bit 5. Port C bit 6. Port D bit 7. Port D bit 0. Port D bit 1. Port D bit 2. Port D bit 3. Port D bit 4. Port D bit 5. External loop filter pin, a capacitor is connected between this pin and analog ground USB DPLUS pin USB DMINUS pin XTAL oscillator input pin XTAL oscillator output pin Analog 3.3V Analog ground
USB
DPLUS DMINUS XTAL1 XTAL2 AVDD AVSS VSS
IO IO I O P P P
99 100 113 114 101/105 102/104
XTAL
Power
Power
18/47/92/ Digital ground pin 115/3/33/ 64/4/8
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Function Signal Name VDD IO P Pin Number 48/66/91/ 116/32/63/ 75/2/7 5 15 81 83 10 11 Description Digital 3.3V
RST ALE EA PSEN SELCLK SEL1 SEL2
I O I O I I
System reset pin, Shmmit trigger External address latch enable pin Enable external ROM mode, disable internal FLASH External ROM data output enable CPU clock select pin 1 CPU clock select pin 2
Note :
- - - - - After reset, all extra function is disabling. When extra function enable, that I/O is in input or output mode is dependent on pin function. Ports are GPIO and input after reset, and still a GPIO if the extra function does not turn on by software. The initial state of GPIO is High, LOW, or TRI-STATE, which is dependent on I/O cell as IO_PU, IO_PD or IO_TR. SEL [2:1]=00, 01, or 10 CPU clock is 12Mhz, 24Mhz or 48Mhz. SEL [2:1]=11 is reserved. Connect 1.2 Mohm between XTAL1 and XTAL2.
Connect 820 pF between FILTER and VSS.
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3. FUNCTION DESCRIPTION
IC1110 includes a turbo 80T32 CPU core, 32K-byte internal program Flash-ROM, 5.5-bytes SRAM and many interface blocks. Including USB function, CF/SM/MMC/SD/MS flash card interface, IBM micro drive interface, IDE hard disk interface, UART, NAND type flash chip interface, SDRAM interface, I2C master & slave blocks, high speed parallel port master & slave interface and MP3 decoder interface. If turning on extra function, the data can be shared through central control block as Figure 1. Data can be transferred very effective and result a best performance in card reader and other application. The IC1110 embedded full speed USB port as major bridges to talk to other host. IC1110 also provides both master and slave parallel port, UART port and I2C port for any extended function usage. For those early development or code always changing environment, IC1110 provides a flexible solution with embedded 32K bytes program Flash-ROM. User can update her/his ROM code by our built in ISP function. IC1110's ISP function gives customer three different choices to take, via USB and I2C. IC1110 can support CPU data memory space up to 5.5K bytes by turning off central control block. For that huge data RAM consumed application, IC1110 will give customer another external 32Mbytes space via bank access method, 32K bytes for each bank. This extra space can still be accessed by executing "MOVX" command and pins of P0 and P2 are still general I/O. In external ROM/SRAM functions pins of P0 and P2 are still available as address and data. User only needs to take care address map without overlap. For those more I/O ports required applications, IC1110 can provide up to 94 general I/O pins.
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Figure 1. System block diagram
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4. ABSOLUTE MAXIMUM RATINGS
Parameter Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Notes 1. Operating temperature is for commercial product defined by this spec. 2. Minimum D.C. input voltage is -0.5 V. During transitions, inputs may undershoot ,to -2.0 V for periods less than 20 ns. Maximum D.C. voltage on output pins is VCC+0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. Rating 0 to +70 -65 to +125 3.0 to 3.6 Unit (1) V (2)
Warning
Stressing the device beyond the "Absolute Maximum Rating" may cause permanent damage. This is stress rating only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability.
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5. OPERATING CONDITION
Recommended Operating Conditions (TA = 0 to 70 C)
Symbol VDD Vil Vih CLOCK Signal Filter Cap Parameter Power supply voltage(reference to VSS PIN) Input low voltage of all GPIO PAD Input high voltage of all GPIO PAD Clock input frequency at XTAL1 PLL filter capacitor Min 3.0 -0.5 2.0 12-30ppm 779 TYP 3.3 0 3.3 12 820 Max 3.6 0.8 5.5 12+30ppm 861 Unit V V V MHz pF
Operating ranges define those limits between which the functionality of the device is guaranteed.
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6. DC ELECTRICAL CHARACTERISTICS
DC Characteristics (3.3V +/- 0.3 V, 12MHz, TA= 25C)
Symbol Vol. Voh Vol(USB) Voh(USB) Iil,Iih Iil Iih Ru Rd Vdr Parameter Output low of all GPIO Output high of all GPIO Static OUTPUT Low Static OUTPUT High Input leakage current for All Tri-State GPIO Input leakage current for All IO_PU GPIO Input leakage current for All IO_PD GPIO IO_PU pull up resistor IO_PD pull down resistor Minum voltage to keep RAM data Min 2.4 2.8 -10 0.3 3.6 10 -75 75 150 150 TYP Max 0.4 Unit V V V V uA uA uA K K V Test condition Iol = 4mA Ioh = 4mA RL=1.5K 3.6V RL=1.5K 3.6V Vin=0 or 3.6 V Vin=0 Vin=3.6 V
50 50 2
100 100
Current Consumption
Icc Active current 12 MHz 24 MHz 48 MHz Idle current 12MHz 24MHz 48MHz Power down current 20 30 55 18 28 48 80 mA Vcc = 3.6V
Icci
mA
Vcc = 3.6V
Ipd
uA
Vcc = 3.6V
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7. AC SPECIFICATION
In order to maintain compatibility with the original 8051 family, this device specifies the same parameter for each device, using the same symbols. The explanation of the symbols is as follows.
t C H I Q V X Time Clock Logic level high Instruction Output Data Valid A D L P R W Address Input Data Logic level low
PSEN
RD signal WR signal
Tri-state
No longer a valid state Z
The following tables are defined under following condition:
Ta=0 to 70; Vcc=3.3V 10; Vss=0V; Cl for port 0, ALE and PSEN Outputs=100 pF; Cl for other outputs=80 pF
7.1
ECTERNAL MEMORY CHARACTERISTICS
PARAMETER
SYMBOL
Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low or MOVX WR ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width
PSEN Low to Valid Instruction In
1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ
VARIABLE CLOCK MIN 3.5 1.5tCLCL - 6 0.5tCLCL - 6 0.5tCLCL - 6 0.5tCLCL - 6 2.0tCLCL - 6 0 -
VARIABLE CLOCK MAX 40 2.5tCLCL - 20 2.0tCLCL - 20 1.0tCLCL - 6 3.0tCLCL - 20 5
UNITS
MHz ns ns ns ns ns ns ns ns ns ns ns
Input Instruction Hold After PSEN Input Instruction Float After PSEN Address to Valid Instr. In PSEN Low to Address Float
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7.2 MOVX CHARACTERISTICS USING STRECH MEMORY CYCLES
PARAMETER Address Hold After ALE low for MOVX WR RD Pulse Width
WR Pulse Width
SYMBO L tLLAX1 tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV
VARIABLE CLOCK MIN 0.5tCLCL - 6 2.0tCLCL - 10 tMCS - 10 2.0tCLCL - 10 tMCS - 10 0 -
VARIABLE CLOCK MAX 2.0tCLCL - 20 tMCS - 20 tCLCL - 6 2.0tCLCL - 6 2.5tCLCL - 20 tMCS - 20 3.0tCLCL - 20 tMCS +2.0tCLCL 20 0.5tCLCL + 6 1.5tCLCL + 6 0.5tCLCL - 6 10 1.0tCLCL + 10
UNIT S ns ns ns ns ns ns ns ns
STRECH tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0
RD Low to Valid Data In Data Hold after RD Data Float after RD ALE Low to Valid Data In Port 0 or Port 2 Address to Valid Data In ALE Low to RD or WR Low Port 0 or Port 2 Address to RD or WR Low Data Valid to Transition Data Hold after WR
WR
tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH
0.5tCLCL - 6 1.5tCLCL - 6 tCLCL - 10 2.0tCLCL -10 -5 tCLCL - 10 tCLCL - 10 2.0tCLCL - 10 0 1.0tCLCL - 10
ns ns ns ns ns ns
RD Low to Address Float RD or WR high to ALE high
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of tMCS for each selection of the stretch value. M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 MOVX machine cycles 2 3 4 5 6 7 8 9 tMCS 0 4 tCLCL 8 tCLCL 12 tCLCL 16 tCLCL 20 tCLCL 24 tCLCL 28 tCLCL
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7.3 SERIAL PORT MODE 0 TIMING CHARACTERISTIC
PARAMETER Serial Port Clock Cycle Time SM2=0 -> 12 clocks per cycle SM2=1 -> 4 clocks per cycle Output Data Setup to Clock Rising Edge SM2=0 -> 12 clocks per cycle SM2=1 -> 4 clocks per cycle Output Data Hold to Clock Rising Edge SM2=0 -> 12 clocks per cycle SM2=1 -> 4 clocks per cycle Input Data Hold after Clock Rising Edge SM2=0 -> 12 clocks per cycle SM2=1 -> 4 clocks per cycle Clock Ring Edge to Input Data Valid SM2=0 -> 12 clocks per cycle SM2=1 -> 4 clocks per cycle
7.4
SYMBOL tXLXL
MIN 12tCLCL-10 4tCLCL-10 10tCLCL-10 3tCLCL-10 2tCLCL-10 tCLCL-10 tCLCL tCLCL -
MAX 12tCLCL+10 4tCLCL+10 11tCLCL 3tCLCL
UNITS ns
tQVXH
ns
tXHQX
ns
tXHDX
ns
tXHDV
ns
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time
SYMBOL tCHCX tCLCX tCLCH tCHCL
VCC- 0.5 V
MIN 8 8 -
TYP -
MAX 5 5
UNITS ns ns ns ns
0.7VCC 0.2VCC - 0.1V TCLCX TCHCL TCLCL TCHCX TCLCH
0.45V
Figure 32. External clock drive waveform
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8. TIMING DIAGRAM
8.1
PROGRAM MEMORY READ CYCLE
t LHLL t LLIV
ALE
t AVLL
PSEN
t PLPH t PLIV t LLPL t PLAZ t LLAX t PXIZ t PXIX
INSTRUCTION IN
AVIV
PORT 0
ADDRESS A0 - A7
ADDRESS A0 - A7
t
PORT 2
ADDRESS A8-A15
ADDRESS A8-A15
Figure 3. Program memory read cycle
8.2
DATA MEMORY READ CYCLE
ALE
t LLDV t WHLH
PSEN
t LLWL t LLAX1
t RLRH t RLDV t RHDZ
RD
t AVLL t AVWL t RLAZ
ADDRESS A0 - A7
t RHDX
DATA IN ADDRESS A0 - A7
PORT 0 INST. IN
t AVDV
PORT 2 ADDRESS A8-A15
Figure 4. Data memory read cycle
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8.3 DATA MEMORY WRITE CYCLE
ALE
t WHLH
PSEN
t LLWL t LLAX1 t WLRH t WHQX
ADDRESS A0 - A7 DATA OUT ADDRESS A0 - A7
WR PORT 0 INST. IN
t AVLL t AVWL
t QVWX
PORT 2 ADDRESS A8-A15
Figure 5. Data memory writes cycle
8.4
DATA MEMORY WRITE WITH STRECH = 0
Last Cycle of Previous Instruction First Machine Cycle Second Machine Cycle Next Instruction Machine Cycle
MOVX instruction cycle C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK ALE PSEN WR PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Inst. Address MOVX Inst.
Next Instr. Address Next Instr. Read
MOVX Data Address
MOVX Data out
PORT 2
A15-A8
A15-A8
A15-A8
A15-A8
Figure 6. Data memory write with strech=0
Integrated Circuit Solution Inc.
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Version 1.0
IC1110-F128LQ USB Flash Card Reader Controller
8.5 DATA MEMORY WRITE WITH STRECH = 1
Last Cycle of Previous Instruction First Machine Cycle Second Machine Cycle MOVX instruction cycle C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 Third Machine Cycle Next Instruction Machine Cycle
CLK ALE PSEN WR PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Inst. Address MOVX Inst.
Next Instr. Address Next Instr. Read
MOVX Data Address
MOVX Data out
PORT 2
A15-A8
A15-A8
A15-A8
A15-A8
Figure 7. Data memory write with strech=1
8.6
DATA MEMORY WRITE WITH STRECH = 2
Next Instruction Machine Cycle
Last Cycle of Previous Instruction
First Machine Cycle
Second Machine Cycle
Third Machine Cycle
Fourth Machine Cycle
MOVX instruction cycle C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK ALE PSEN WR PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Inst. Address
MOVX Inst.
Next Instr. Address Next Instr. Read
MOVX Data Address
MOVX Data out
PORT 2
A15-A8
A15-A8
A15-A8
A15-A8
Integrated Circuit Solution Inc.
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Version 1.0
IC1110-F128LQ USB Flash Card Reader Controller
Figure 8. Data memory write with strech=0
8.7
SERIAL PORT MODE 0 TIMING
Serial Port (Synchronous Mode) High Speed Operation SM2=1 => TxD Clock = XTAL/4
ALE PSEN SBUF write TRANSMIT D7 TxD Clock RxD Data Out TI Clear RI D0 D1 D2 D3 D4 D5 D6 RECEIVE RxD Data In TxD Clock RI
t XLXL
D0 D1
t QVXH
D2 D3
t XHQX
D4 D5 D6 D7
t XHDV
t XHDX
Figure 9. Serial port mode 0 timing at high speed operation
Serial Port (Synchronous Mode) Standard Operation SM2=1 => TxD Clock = XTAL/12
Integrated Circuit Solution Inc.
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Version 1.0
IC1110-F128LQ USB Flash Card Reader Controller
ALE PSEN SBUF write TxD Clock RxD Data Out TI Clear RI TxD Clock RxD Data In RI RECEIVE TRANSMIT D7
t QVXH
D0
t XHQX
D1 D2
t XLXL
D7
t XHDV
D0 D1
t XHDX
D2 D6
Figure 10. Serial port mode 0 timing at standard operation
8.8
CARD INTERFACE TIMING
Figure 11 Parallel port read/write timing
Integrated Circuit Solution Inc.
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Version 1.0
IC1110-F128LQ USB Flash Card Reader Controller
Figure 12
CF card read/write timing
Figure 13
SM card read/write timing
Integrated Circuit Solution Inc.
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Version 1.0
IC1110-F128LQ USB Flash Card Reader Controller
Figure 14
MMC/SD card read/write timing
Figure 15 MS card read/write timing
Figure 16
MP3 output timing
Integrated Circuit Solution Inc.
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Version 1.0
IC1110-F128LQ USB Flash Card Reader Controller
Integrated Circuit Solution Inc.
24
Version 1.0
IC1110-F128LQ USB Flash Card Reader Controller
ORDERING INFORMATION COMMERCIAL TEMPERATURE : 0 oC to +70 oC Order Part Number IC1110-F128LQ Package 14*14*1.4mm LQFP
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 FAX: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5 TH ROAD HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
25
Version 1.0

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